An integrated circuit is typically formed on a substrate by the sequential deposition of conductive, semiconductive or insulative layers on a silicon wafer. One fabrication step involves depositing a filler layer over a non-planar surface, and planarizing the filler layer until the non-planar surface is exposed. For example, a conductive filler layer, such as copper, can be deposited on a patterned insulative layer to fill the trenches or holes in the insulative layer. The filler layer is then polished until the raised pattern of the insulative layer is exposed. After planarization, the portions of the conductive layer remaining between the raised pattern of the insulative layer form vias, plugs and lines that provide conductive paths between thin film circuits on the substrate. In addition, planarization is needed to planarize the substrate surface for photolithography.
CMP is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against a rotating polishing disk pad or belt pad. The polishing pad can be either a “standard” pad or a fixed-abrasive pad. A standard pad has a durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment medium. The carrier head provides a controllable load on the substrate to push it against the polishing pad. A polishing solution, including at least one chemically-reactive agent, is supplied to the surface of the polishing pad. The polishing solution can optionally include abrasive particles, e.g., if a standard pad is used.
A variation of CMP, which is particularly useful for copper polishing, is ECMP. In ECMP techniques, conductive material is removed from the substrate surface by electrochemical dissolution while concurrently polishing the substrate, typically with reduced mechanical abrasion as compared to conventional CMP processes. The polishing solution includes an electrolyte. The electrochemical dissolution is performed by applying a bias between a cathode and the substrate surface and thus removing conductive material from the substrate surface into the surrounding electrolyte solution.
In both CMP and ECMP, a polishing solution is applied to a rotating surface. Due to centrifugal forces, the polishing solution disperses across the surface of the polishing pad, causing much of it to spill over the edge of the pad before its functional capacity is exhausted. These polishing solutions are expensive consumables. The per substrate cost of these processes could be reduced considerably by reducing the amount of polishing solution used. In addition, as the polishing pad's angular velocity is increased, smoother substrate surfaces and increased substrate planarization efficiency and consistency from center to edge result. Increased angular velocity, however, leads to stronger centrifugal forces, which lead to more polishing solution spillover.